Signature analysis is a circuit test method which generates a nearly unique data code or signature at a circuit node with the electrical signal at that node modifying a pseudo random sequence during a selected period of time. See, for example, U.S. Pat. No. 3,976,864 issued on Aug. 24, 1976 to Gordon et al.
Previous use of signature analysis test systems has required the operator to determine which node to test, obtain a signature from that node, and then compare the signature obtained to the expected value for that node. The operator had to keep track of the nodes tested and perform the various clerical tasks necessary, such as, matching up the designation of the node on the schematic and the assembly under test, determining the signature of the specific node under test, and then comparing the signature actually obtained with the one that should have been obtained at that node. On large assemblies particularly, this clerical overhead increases probability of operator error.
Some previous systems have attempted to reduce this clerical overhead by using "guided test probe" techniques. These techniques require the operator to strictly follow a preset sequence. They also have the disadvantage that the operator must follow the predetermined guided test node sequence and therefore cannot follow his suspicions and test the board areas in the order he feels they are most likely to contain the faulty component in view of the indicated symptoms placed on the repair tag by field service or assembly line personnel.
In accordance with the preferred embodiment of the present invention, a circuit test system using signature analysis techniques contains a list of acceptable signatures which could be obtained from a corresponding assembly if it was in proper working condition. During testing of an assembly, the operator randomly probes test nodes of the assembly to obtain signatures. Once the signature is obtained, the system searches through the list to see if a match can be found between the signature obtained from the assembly under test and those in the list. If a match is found, a pass indication is provided. Correspondingly, if no match if found, a fault indication is provided.
The probability that the signature for a fault node might match with the good signature for another node is quite low. The possibility that a bad board could completely test good is further lessened when one realizes that errors propagate through a circuit and there would typically be several bad signatures on a malfunctioning board.